A. Field of the Invention
The present invention relates to a MIS (Metal-Insulator-Semiconductor) type semiconductor device having a trench gate structure.
B. Description of the Related Art
FIG. 48 is a cross-sectional view showing a configuration of a MIS-type field effect transistor (FET) having a conventional trench gate structure. As shown in FIG. 48, in the conventional vertical trench gate-type n-channel MISFET, p-base region 2, n+-source region 3 and p+-contact region 4 are formed on a first principal surface side across n-drift region 1, while n+-drain region 5 is formed on a second principal surface side across n-drift region 1. Gate insulator 6 and gate electrode 7 are formed in trench 8 that extends from the first principal surface through p-base region 2 into n-drift region 1.
Source electrode 9 is electrically connected to n+-source region 3 and p+-contact region 4, and insulated from gate electrode 7 by interlayer insulator 10. Drain electrode 11 is electrically connected to n+-drain region 5. In FIG. 48, the broken line indicated by reference number 12 in p-base region 2 and the broken line indicated by reference number 13 in n-drift region 1 represent edges of a depletion layer when the MISFET is in the off-state.
FIG. 49 is a characteristic chart schematically showing the distribution of electric field strength at A-A′ shown in FIG. 48. Reference characters B1, B2 and B3 on the ordinate axis in FIG. 49 correspond to edge 12 (B1) of the depletion layer in p-base region 2, pn junction 14 (B2) between p-base region 2 and n-drift region 1, and edge 13 (B3) of the depletion layer in n-drift region 1, respectively, at A-A′ shown in FIG. 48. The withstand voltage of the MISFET corresponds to the area of the electric field distribution when the maximum electric field strength reaches a critical electric field strength in the characteristic chart shown in FIG. 49.
To reduce the gate-drain capacitance, it is known to provide thick SiO2 on the bottom of the trench of the MISFET-type semiconductor device (see U.S. Patent Application Publication No. 2004/0166636, FIG. 3, for example). To reduce the gate-drain capacitance, it is also known to provide an oxide film under the gate electrode in the MISFET having a super junction structure in which a p-type impurity layer is provided adjacent to the n-drain/drift region (see U.S. Pat. No. 5,981,996, FIG. 1, for example). There is also a known semiconductor device provided with a field formation region made of SiO2, Si3N4, Ta2O5, SrTiO3, or BaTiO3 across the n-drain/drift region and the p-body that form a pn junction (see WO 2004/102670, FIG. 7, for example).
There is also a known semiconductor device having a structure in which the lower part of the trench is filled with SiO2 while the upper half of the trench is provided with the gate electrode (see JP-A-2005-302925, FIG. 1, for example). There is also a known transistor having a structure in which a dielectric layer made of SiO2 or Si3N4 is provided under the gate electrode and a field plate is provided adjacent to the dielectric (see JP-A-2003-204064, FIGS. 4 and 5K, for example).
There is a need to reduce on-resistance in MIS-type power semiconductor devices, such as power MOS (Metal-Oxide-Semiconductor) FETs and IGBTs (Insulated Gate Bipolar Transistor). However, in the semiconductor device disclosed in U.S. Patent Application Publication No. 2004/0166636, it is apparent from the document that the thick SiO2 on the bottom of the trench does not contribute to reduction in on-resistance. Therefore, although extending the N-epitaxial layer (drift region) may reduce its concentration, it increases the proportion of the resistance of the N-epitaxial layer (drift region) relative to the total on-resistance, so that an increased number of gate electrodes by employing the trench gate structure unfortunately cannot achieve sufficient reduced on-resistance as the whole device.
In the semiconductor device disclosed in U.S. Pat. No. 5,981,996, reducing on-resistance by providing the p-type impurity layer adjacent to the n-drain/drift region is contemplated, but the oxide film under the gate electrode does not contribute to reduction in on-resistance. When the numbers of carriers in the n-drain/drift region and the p-type impurity layer are not balanced, the depletion layer will not expand due to residual carriers in the off-state, resulting in reduced withstand voltage. To achieve desired complete depletion, it is necessary to precisely control the impurity concentrations in the n-drain/drift region and the p-type impurity layer.
In the semiconductor device disclosed in WO 2004/102670, as the field formation region is an idle region where no on-current flows, provision of the field formation region increases the width of a unit element, disadvantageously resulting in lower integration level. Furthermore, to fabricate this semiconductor device, it is necessary to form a trench for the gate electrode as well as a trench for the field formation region that is deeper than the gate electrode trench with these trenches tightly close to each other and separately fill these trenches, unfortunately resulting in very difficult fabrication.
In WO 2004/102670, simulation results on a diode structure are also disclosed (WO 2004/102670, FIG. 4). However, according to a study conducted by the inventors, it has been found that the structure shown in FIG. 7 in WO 2004/102670 would hardly provide effects comparable to the simulation results. The reasons for this follow.
In the structure shown in FIG. 3A in WO 2004/102670, the pn junction is formed by p-region and n-region of the same concentration, so that the depletion layer will sufficiently expand into both the p-region and n-region in the off-state. In contrast, in the structure shown in FIG. 7 in WO 2004/102670, the pn junction is formed by the p-body of high concentration and the n-drain/drift region of low concentration, so that the depletion layer expands only into the n-drain/drift region.
Even if the depletion layer is forced to expand into the p-body, the depletion layer will reach the source region, resulting in punch through. To avoid this, even if the p-body is extended to ensure a sufficient range for depletion layer expansion, the equipotential surface in the area around the gate electrode, which is located on the surface opposite to the field formation region on the pn junction, is pushed into the n-drain/drift region, so that desired expansion of the depletion layer comparable to the extension of the p-body cannot be achieved. Conversely, there is created an undesired portion around the gate electrode where the electric field concentrates, disadvantageously resulting in reduced withstand voltage. Furthermore, the extended p-body increases the length of the channel, disadvantageously resulting in increased on-resistance.
In the semiconductor device disclosed in JP-A-2005-302925, it is necessary to increase the thickness of the drift layer in order to increase the source-drain withstand voltage. To maintain or reduce on-resistance even when the drift layer is thicker, it is necessary to increase the gate drive voltage to be comparable to the source-drain withstand voltage or even higher. In the semiconductor device disclosed in JP-A-2003-204064, provision of the field plate disadvantageously prevents higher integration level.
To solve the above problems associated with the related art, an object of the invention is to provide a semiconductor device capable of ensuring the withstand voltage without changing the thickness of the drift layer and reducing on-resistance without applying a high gate drive voltage. Another object of the invention is to provide a method for easily manufacturing a semiconductor device having such properties.
The present invention is directed to overcoming or at least reducing the effects of one or more of the problems set forth above.